1. Field of the Invention
The present invention relates to a high voltage metal oxide semiconductor (HV MOS) transistor, and more particularly, to an HV MOS transistor used in electrostatic discharge protection circuits.
2. Description of the Prior Art
As the density of very large scale integrated (VLSI) circuit increases, the components of the circuits are getting smaller and smaller. When the gate oxide of the MOS transistor gets thinner and thinner, it becomes increasingly easy for the gate oxide to be destroyed by electrostatic discharge (ESD) . In order to prevent an excessive current from entering an IC via an I/O pin and destroying the internal circuitry of the IC, a protection circuit is usually installed between the internal circuitry and the I/O pin. The protection circuit must activate before the pulse of an electrostatic discharge can reach the internal circuitry so as to instantly eliminate the high voltage of the pulse. Consequently, the protection circuit must use HV MOS transistors to guarantee that the protection circuit can operate correctly under high voltages and prevent the destruction caused by ESD.
Please refer to FIG. 1. FIG. 1 is a circuit diagram of a prior art ESD protection circuit 10. The prior art ESD protection circuit 10 is installed between an internal circuit 11 and a bonding pad 12. The bonding pad 12 is used to connect to an I/O pin (not shown) in the following-up packing process. The ESD protection circuit 10 comprises an input port 13, a 30 volt voltage source 14, a grounding point 15, a first N-type HV MOS transistor 16, a P-type HV MOS transistor 17, and a second N-type HV MOS transistor 18. The input port 13 is electrically connected to the internal circuit 11 and the bonding pad 12. The HV MOS transistor 16 is electrically installed between the input port 13 and the grounding point 15. The first HV MOS transistor 17 is electrically installed between input port 13 and the voltage source 14. The HV MOS transistor 18 is electrically installed between the grounding point 15 and the voltage source 14, and is electrically connected to the HV MOS transistor 17. In each HV MOS transistor the source, well (or substrate), and drain form a parasitic bipolar junction transistor (BJT). The threshold voltage of the parasitic bipolar junction transistor (BJT) is smaller than the breakdown voltage of the gate in the internal circuit 11. The parasitic bipolar junction transistor (BJT) will turn on before the electrostatic discharge pulse reaches the internal circuit 11, and so serves to protect the gate of the internal circuit 11 from excess voltage and current surges.
An input voltage from the bonding pad 12 will be delivered into the internal circuit 11 via the input port 13 of the ESD protection circuit 10. When the input voltage exceeds the threshold voltage of the BJT transistor inside the HV MOS transistors 16, 17, and 18, the HV MOS transistors 16, 17 and 18 will conduct the large current caused by the high voltage to the grounded port 15, thereby eliminating the high voltage input from the input port 13. For example, if the input voltage is negative, the P-type HV MOS transistor 17 and the second N-type HV MOS transistor 18 will turn on in turn to divert the current caused by the negative voltage to the grounded port 15, and so reduce the voltage input into the internal circuit 11. Similarly, if the input voltage is positive, the first N-type HV MOS transistor 16 will turn on to reduce the voltage via the grounded port 15.
Please refer to FIG. 2. FIG. 2 is a cross-sectional diagram of the structure of the first N-type HV MOS transistor 16 used in the ESD protection circuit 10 shown in FIG. 1. The first and second N-type HV MOS transistors 16, 18 of the prior art ESD protection circuit are formed on a semiconductor wafer 20. In the following explanation, the first N-type HV MOS transistor 16 is taken as an example to explain the structure of the HV MOS transistors 16, 18 in the prior art ESD protection circuit 10. The semiconductor wafer 20 comprises a substrate 22, an active region 24 installed in a predetermined area on the surface of the substrate 22, and a first insulation layer 26 made of field oxide (FOX) installed on the surface of the substrate 22 and surrounding the active region 24. The active region 24 comprises a P-type doped area 28 that serves as a P-well.
The prior art first N-type HV MOS transistor 16 comprises a gate 30 installed on the active region 24, a source 32 and a drain 34 installed in the doped area 28 of the active region 24 and positioned on opposite sides of the gate 30, a second insulation layer 36 made of field oxide installed on the active region 24 and positioned between the gate 30 and the source 32 and between the gate 30 and the drain 34, and a drift region 38 installed at the intersection of the doped area 28 of the active region 24 and the second insulation layer 36. The drift region 38 acts as an n-drift region. Both the source 32 and the drain 34 are double diffuse drains (DDD) 40 comprising an N-type doped area 33. The gate 30 is made by stacking a doped polysilicon layer 42 on top of a gate oxide layer 44. The second insulation layer 36 is used for insulating the gate 30 from the source 32 as well as insulating the gate 30 from the drain 34.
The structure of the P-type HV MOS transistor 17 and the structure of the first, second N-type HV MOS transistors 16, 18 are the same except that the dopants of the doped areas are different. The doped area 28 in the active region 24 of the P-type HV MOS transistor 17 is an N-well, the drift region 38 is a p-drift region, and both the double diffuse drains (DDD) 40 of the source 32 and the drain 34 comprise a p-type doped area.
Currently, HV MOS transistors comprise a doped area of n-drift or p-drift, which is used to solve the problem that the channel length of the HV MOS transistor is too long to promote conduction between the components. So, every HV MOS transistor on the substrate 22 of the semiconductor wafer 20, including HV MOS transistors 16, 17 and 18, has a drift region 38 at the intersection of the doped area 28 of the active region 24 and the second insulation layer 36. However, because the drift region 38 of the prior art HV MOS transistor is protruding from the double diffuse drains 40, the drift region 38 has a higher horizontal electrical field and causes tip effects. In other words, when a high voltage is delivered into the HV MOS transistors 16, 17 and 18, a strong horizontal electrical field can easily be generated inside the path and emit main carriers (electrons are the main carriers of the N-type HV MOS transistor, and holes are the main carriers of the P-type HV MOS transistor) directly from the source 32 via the drift region 38 into the drain 34, rather than along the path from the source 32 to the doped area 28 of the active region 24 to the drain 34. This causes short circuiting between the source 32 and the drain 34 and destroys the structure of the gate oxide layer 44, preventing the BJT transistor from turning on to discharge the high voltage.